1. Field of the Invention
The present invention relates to a high speed single plane dynamic decoder which may be easily programmed by adding or deleting series terms.
2. Background of the Invention
A logic array can be implemented in a variety of ways. Typically, the required logic equation is reduced to as close to minimum complexity as possible and then the actual circuit logic to implement the equation is selected. Classically, the circuitry used is multi-input NAND, NOR or complex gates connected to achieve the desired logic result.
There are a number of drawbacks to the classic approach. The logic is usually cumbersome to lay out on an integrated circuit chip since each logic gate is typically different in size, making packing difficult. In addition, the interconnects between logic elements become very extensive when logic levels grow in size. Also, after packing the logic, any design changes required to be made in the logic circuit are difficult to implement at best and often the entire layout must be redone. Furthermore, the actual silicon area required to hold the logic array can become quite large, thus increasing costs and decreasing yield. An additional problem is that propagation delays through the static array increase with each logic level and can become quite large when the logic required is complex.
The speed through the decorder is of utmost importance when designing a high speed processor or controller that must decode instructions or control lines.
FIG. 1 shows a classic NAND-NAND static decoder. The transistor count of this static approach is 24 total CMOS transistors.